1. Field of Invention
The present invention relates to non-volatile semiconductor memory apparatuses, and more particularly to non-volatile semiconductor memory apparatuses equipped with charge pump devices that step up power supply voltage.
2. Description of Related Art
Semiconductor memory apparatuses may be classified into a variety of different types depending on their functions. Such semiconductor memory apparatuses includes a memory cell array that is formed of memory cells arranged in a matrix. In general, an address in a row direction and a column direction in the memory cell array is designated in performing a reading, programming or erasing operation for each of the memory cells.
By controlling voltages applied to a signal line in the row direction and a signal line in the column direction that are connected to each of the memory cells, a specified memory cell can be accessed, such that a specified operation among reading, programming and erasing operations thereof can be performed. In other words, in order to select a specified memory cell, a voltage different from other voltages to be applied to other memory cells may be generated from the power supply voltage and applied.
Recently, MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -substrate) type devices have been developed as non-volatile semiconductor devices that are electrically erasable and have non-volatility. A MONOS type non-volatile semiconductor memory apparatus has memory cells that each have two memory elements, as described in detail in a publication (Y. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-p.123).
As described in this publication, to access each of the memory elements of the MONOS type non-volatile semiconductor memory apparatus via signal lines (control lines) that are provided according to the number of the memory cells, not only two kinds of voltage values, but a plurality of kinds of voltage values need to be set for each of the signal lines (control lines).
In this case, devices that each have a pair of a charge pump circuit that operates with the power supply voltage and a regulator may be prepared in the number of kinds of voltages required for each of the operations of the memory.
The response of the charge pump is slow due to restrictions of its clock frequencies and the like. Accordingly, when the operation of the charge pump circuit is stopped in a standby mode, it takes a long time, after shifting to an active mode, in particular when shifting to a read that requires a high voltage, to reach an accessible state.
In this respect, the charge pump may be operated even during a standby mode, and a high voltage is maintained by the charge pump, and a regulator may be used to generate required operation voltages.
However, the amount of current that circulates in the charge pump and a regulator that generates operation voltages to read in particular is extremely large. Therefore, it is a problem that the current consumption in the standby mode is high.
The present invention addresses the problems described above, and provides a non-volatile semiconductor memory apparatus that can substantially reduce the current consumption in a standby mode by using a weak charge pump for standby with a small capacity.
A non-volatile semiconductor memory apparatus in accordance with the present invention includes: a charge pump device that steps up a power supply voltage and outputs the same; an operation voltage setting device that sets operation voltages to execute plural modes for a specified non-volatile memory element within a memory array formed of a plurality of non-volatile memory elements; a constant voltage device that is provided with voltages output from the charge pump device to generate the operation voltages; and a weak charge pump device that operates with a current consumption that is lower than the charge pump device in a standby mode to step up the power supply voltage and output the same.
With this structure, the charge pump device steps up the power supply voltage and supplies the same to the constant voltage device. The constant voltage device, at the time of activation, generates operation voltages from the output of the charge pump device, and supplies the same to the operation voltage setting device. The operation voltage setting device uses voltages generated by the constant voltage device to set operation voltages to execute various modes, such as, for example, a read mode, program mode and erase mode. In contrast, at the time of standby, the weak charge pump device steps up the power supply voltage and outputs the same. The weak charge pump device causes a low current consumption, such that the current consumption amount at the time of standby can be markedly reduced. Also, since the stepped up power supply voltage is supplied to the constant voltage device even at the time of standby, the operation voltage can be immediately generated from the constant voltage device, such that a high speed access is possible even in a shift from a standby mode to an active mode.
The weak charge pump device generates a voltage for a read mode for the non-volatile memory element.
With this structure, at the time of reading, high operation voltages and high speed response are required. The weak charge pump device generates a power supply voltage at the time of reading, such that, even when shifting to an active mode, the power supply voltage can be supplied to the constant voltage circuit immediately after the shift and therefore a high speed access is possible.
The charge pump device steps up the power supply voltage to generate a plurality of voltages.
With this structure, the range of voltage values that can be generated by one or a plurality of constant voltage devices can be broadened.
The constant voltage device is capable of generating constant voltages of different voltage values depending on read, program or erase mode for the non-volatile memory element.
With this structure, the constant voltage device can obtain constant voltages according to an operation mode, i.e., a read mode, a program mode or an erase mode. Therefore, when a plurality of operation voltages are required for each of the modes, each mode can be executed.
The non-volatile memory element forms a twin memory cell controlled by one word gate and first and second control gates.
With this structure, for example, a reading operation, a programming operation or an erasing operation can be performed for the memory array with twin memory cells.
The operation voltage setting device sets voltage values provided from the one or the plurality of constant voltage devices independently for the first and second control gates, and an impurity layer to access trapped charge of the non-volatile memory element.
With this structure, the operation voltage setting device sets operation voltages required for a word gate that selects a twin memory cell, sets operation voltages required for the first and second control gates to select a non-volatile memory element within the selected twin memory cell, and sets required operation voltages for an impurity layer to access trapped charge of the selected non-volatile memory element. As a result, for example, a reading operation, a programming operation or an erasing operation can be performed for a specified non-volatile memory element in a specified twin memory cell.
The operation voltage setting device includes: a word line connected to a word gate of the twin memory cell in the same row; a control gate line that is commonly connected to the mutually adjacent first and second control gates in the same column of the twin memory cells arranged adjacent to each other in a row direction; and a bit line that is commonly connected to impurity layers to access trapped charge arranged in the same column of the mutually adjacent non-volatile memory elements of the twin memory cells arranged adjacent to each other in the row direction. Voltages provided from the constant voltage device are set independently for the control gate line and the bit line.
With this structure, the operation voltage setting device selects with the word line twin memory cells in the same row, commonly selects with the control gate line mutually adjacent first and second control gates in the same column of the twin memory cells arranged adjacent to each other in the row direction, and commonly selects with the bit line impurity layers in the same column to access trapped charge of the mutually adjacent non-volatile memory elements of the twin memory cells arranged adjacent to each other in the row direction. As a result, even when a memory array is composed of numerous non-volatile memory elements, sections at which operation voltages are to be set can be reduced.
The non-volatile memory element has an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O) as a charge trap site.
With this structure, operation voltages of an apparatus using a MONOS type non-volatile memory can be set.